1. Field of Use
This invention relates to pipelined data processing systems and more particularly to apparatus for decoding instructions within such systems.
2. Prior Art
Many techniques have been developed in order to improve the performance of high performance systems. These have involved the development of so-called pipelined processors which process instructions stored in cache memories in such a manner that more than one instruction is actually being processed at any one given time. In such a system, one instruction might be completed within a given machine cycle at the same time as another instruction had only been partially completed.
While such systems achieve high performance, instructions are placed serially into the pipeline and as soon as the stage has completed its operation, the instruction is passed onto the next processing stage. Therefore, instructions are executed in the order in which they enter the pipeline. In order to improve system performance, some systems overlap the operations being executed by certain stages within the pipeline. An example of this type of system is described in U.S. Pat. No. 4,760,519.
While the above improves performance, instructions are still required to be executed in the order in which they are introduced into the pipeline. The performance of a pipelined system has been improved by having the processing unit operate in a production line fashion in which earlier stages are able to complete the execution of certain types of instructions ahead of earlier introduced instructions. This processing unit is subject of related copending application titled "Production Line Method and Apparatus for High Performance Instruction Execution."
While pipelined processing units provide high performance, their performance still depends greatly on the efficient processing of a large number of different types of instructions. This is complicated when there is a requirement for compatibility and where more than one stage within the pipeline is designed to execute instructions to enhance performance such as in the referenced patent application.
One approach used in handling a complex instruction set which is described in U.S. Pat. No. 4,179,736 is to use a microprogrammed data processing unit having first and second control stores and hardwired sequence circuits. The first control store includes locations which store address and control sequence fields while the second control store includes sequences of microinstructions for executing different portions of the operations specified by the program instructions. The control sequence field is used to designate which one of a number of hardware control sequences is to be carried out by the hardwired control circuits in processing the instruction through the use of control state circuits.
While this arrangement is capable of processing a complex instruction set, the two-level control store arrangement requires additional processing time and space which do not lend themselves to VLSI construction. Further, the arrangement is designed for use in a CPU containing a small number of pipeline stages having a single execution unit.
Accordingly, it is a primary object of the present invention to provide apparatus for managing the processing of a complex instruction set within a pipelined processing unit.
It is another object of the present invention to provide a method and apparatus which maximizes performance and requires a minimum of complexity.